ESPROS Photonic CMOS^® Process

The key to our outstanding optical detector performance is our own, advanced wafer processing technology. The baseline of this process is an industry standard, well established 150nm CMOS process featuring 1.8V and 5V devices. This process is adapted to incorporate the necessary new devices for optical detectors, while keeping the impact on the available devices as low as possible. Established IP for the 1.8V devices of the baseline PDK can therefore easily be incorporated.

The process adjustments target the extension of the 5V devices for high voltage switching by implementing 12V class drain extended devices. Specific  adaptions to the implants enable another key factor: Backside Illumination! At the core of the modification is the seamless incorporation of a CCD module in the CMOS process flow without any compromise on the reference device parameters.

As a result, the combination of state-of-the art low voltage digital devices (1.8V, L_Gate=150nm), 5V high-performance analog transistors (L_Gate=550nm) and the 12V extension make very complex System on chip applications possible. Typically, our products integrate significant digital processing, A/D conversion, active power / voltage regulation in several voltage domains.

Additionally, a proprietary non-volatile memory solution is implemented to seamlessly fit our process. This NVM is used to store system configuration parameters for the complex SOCs that are already implemented in the technology.

Process profile